Integrated circuit complexity has continued to evolve, placing increasingly more demanding specifications on the processes used in their manufacture. As the requirement for increasing the density of active devices on an individual chip has escalated, the requirement for greater flatness, over long distances and short distances, on the surfaces, top and bottom, of the wafer has also evolved. A flat surface is desirable for several reasons. Flatness is a requirement for cooperation with the optical focussing characteristics of optical stepper devices. As the optical lens requirements for increased resolution have increased, the depth of field of the lens has decreased. Also, attachment of the interconnection metallization to its underlayer is improved if the metal is not required to pass over abrupt underlying steps. In addition, flatness improves ability to fill via holes and lines through apertures in the dielectric.
Various processes have been used for planarization. One such process known as Chemical-Mechanical Polishing (CMP) is presently being used in the most demanding applications. CMP enhances the removal of surface material over large distances and short distances by simultaneously abrading the surface while a chemical etchant selectively attacks the surface. For this purpose, CMP utilizes a polishing slurry containing both an abrasive and a chemically active component.
It is known from the prior CMP efforts that for a particular CMP slurry to be successful it must exhibit significantly different removal rates for at least two different materials on the wafer surface. This is called selectivity and is normally shown as a different polish rate for the metal vis-a-vis the interlayer dielectric.
CMP is becoming a preferred method of polishing tungsten during formation of tungsten interconnects and contact/via plugs. A common use of tungsten metal in an integrated circuit is for contact/via plugs. Generally, for this application, a contact/via hole is etched through a dielectric layer to expose regions of the underlying devices (for first-level metallization) or metal interconnects (for higher levels of metallization). A Ti or TiN glue layer is deposited onto the sides and bottom of the contact/via hole, and tungsten is deposited thereon. CMP is used to remove the deposited tungsten from the wafer surface, leaving tungsten plugs in the contact/via holes having surfaces coplanar with the exposed dielectric. With proper process parameters, CMP tungsten processing has shown significantly improved process windows and defect levels over standard tungsten dry etch back processing for this application. One significant advantage of CMP tungsten processing is that it has a highly selective polish rate for tungsten as compared to the dielectric. This selectivity allows for over-polishing while still achieving a flat tungsten plug surface. When overetching using etch-back technology, the contact or via becomes further recessed which creates a serious disadvantage since overetching is frequently required to remove defects and to ensure complete removal of surface tungsten. The advantage of CMP, however, can be offset by the creation of significant levels of defects during polishing, such as scratches. Accordingly, the success of tungsten CMP processing performance for contact/via plug processing as well as tungsten interconnect processing is linked to improvements in selectivity and defect control.
Another important application of tungsten in integrated circuit manufacturing is for so-called local interconnects, conductive straps between circuit elements in close proximity to one another. One commonly used methodology for local interconnects utilizes the Damascene process. In this process a first metal is inlaid into the lowest dielectric layer, usually termed ILD0. This involves first depositing ILD0, then patterning and etching recessed trenches in the dielectric where the metal lines are to be placed. Contact to the underlying devices is made where the trenches pass over the active device regions; elsewhere the field oxide insulates the metal from the substrate. Generally, a sandwich structure of Ti, TiN, and tungsten is next deposited into the trenches and onto the dielectric surface. CMP is used to remove the conductive materials from the dielectric surface, leaving metal stripes in the trenches to function as local interconnects. For this application the CMP process must totally remove all conductive residues of tungsten, TiN, and Ti from the dielectric surface in order to prevent shorting between adjacent metal lines. This is because for the Damascene process, the next process step after CMP is the deposition of next level dielectric, which would leave buried shorts if conductive residues remained. In contrast, for contact/via plug technology, the CMP is followed by next level metal deposition, patterning, and etch, which would remove conductive residues from the dielectric surface during metal overetch. As a result, an optimal CMP process for local interconnects must have high polish rate selectivity of TiN and Ti over dielectric, as well as high polish rate selectivity of tungsten over dielectric. Additionally, the tungsten polish rate and Ti or TiN polish rates would ideally be comparable, so as to avoid erosion of the tungsten lines during Ti or TiN overpolish.
For various reasons, prior CMP slurries have not been as effective as needed. Deep or wide scratch defects of the underlying surface by the abrasive have caused problems. Simultaneous high tungsten and Ti polish rates have only been achieved at the expense of high selectivity to oxide polish rate. Also, since a large volume of CMP slurry is required, the development of a low-cost chemical composition with acceptable shelf life and chemical stability is essential.